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W25Q64FV
6.2.8
Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instructio n code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
Mode 3
0
1
Mode 3
/CS
CLK
Mode 0
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 3
In structio n
CLK
Mode 0
Instruction (04h)
Mode 0
IO 0
04h
DI
(IO 0 )
IO 1
DO
(IO 1 )
High Impedance
IO 2
IO 3
Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
6.2.9
Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “ 35h ” for
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. The Status
Register bits are shown in Figure 4a and 4b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0,
SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when
the cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
Mode 0
Instruction (05h or 35h)
DI
(IO 0 )
DO
(IO 1 )
*
= MSB
High Impedance
7
*
Status Register 1 or 2 out
6 5 4 3 2 1
0
7
*
Status Register 1 or 2 out
6 5 4 3 2 1
0
7
Figure 8a. Read Status Register Instruction (SPI Mode)
- 26 -
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